A Literature Review of On-Chip Network Design with Dynamic Reconfiguration

— The architecture for on chip network design using dynamic reconfiguration is a solution to Communication Interfaces, Chip cost ,Quality of Service, guarantee flexibility of the network. The proposed architecture dynamically configure itself with respect to Hardware Modules such as routers, Packet based Switch and data Packet size by changing the communication conditions and its requirements at rum time. In Noc, we are using Hexagonal node pattern to improve the communication performance. The proposed design avoids the limitations of bus-based interconnection schemes which are often applied in partially dynamically reconfigurable FPGA designs. With the help of this design we can achieve Low latency and high data throughput. In this paper we are reviewing the previous methods and approaches of Dynamic reconfiguration in NOC. IndexTerms — On chip Network, SOC, FPGA, NOC, Router, NI, PE, Dynamic reconfiguration. ——————————  ——————————